FIG. 1 illustrates a prior art method for converting analog audio inputs signals from an analog format to a digital format. The method has a hardware portion 71 and a software portion 75. The hardware portion 75 illustrates a delta/sigma analog to digital (AD) converter 70. The A-D converter 70 receives the analog modulator input signal 68 and converts this signal to a serial stream of binary bits. This serial stream of binary bits is received as input by a third order integrator 72. The integrator 72 performs a low pass filter function and provides a digital data stream which represents the analog input 68. The digital data stream provided as output from the element 72 is decimated to a lower frequency by a rate change switch 73. The decimated data stream is then provided as input to a third order comb filter 74. Element 74 compensates for some frequency distortion introduced by integrator 72. It is important to note the operations performed by element 73 and 74 are performed in software on a digital signal processor. The output of software element 74 is fed to a compensation filter 76. Compensation filter 76 provides for low pass filtering and pass band frequency compensation as is needed in the system. Another rate change switch 77 is used to perform a decimation function similar to that described for rate change switch 73 previously. A software compensation filter 78 then performs a final filtering of the digital signal as is needed. A scaling operation 80 is then used to provide a scaling gain factor 86 which adjusts the magnitude of the filtered digital signal. A side tone operation 82 adds a side tone signal which is obtained through a receive channel 89. The value on the receive channel is scaled by scaling operation 81, which is based upon a side tone scaling gain signal 88. Output 84 is the digital signal output.
In FIG. 1, the A to D converter function 70 is performed in hardware since it is an analog function. In addition, the third order integrator function 72 is performed in hardware since this function requires high frequency operation which may not be possible for a given digital signal processor. The other operations of FIG. 1 are performed in software executed by the digital signal processor since a general purpose digital signal processor can support these operations.
FIG. 2 illustrates a hardware system which can be used to perform the software operations illustrated in FIG. 1. FIG. 2 illustrates a digital signal processor 10. The digital signal processor 10 contains a program control unit (PCU) 12 coupled to an address generation unit (AGU) 14 and to a data operation unit 16. The program control unit 12 contains an instruction register 12B and program control logic 12A as illustrated in FIG. 1. The program control unit 12 is coupled to a program memory unit 18 which is external to the DSP 10. Address generation unit (AGU) 14 is coupled, externally to the DSP 10, to an X data memory 20 and a Y data memory 22. The data operation unit 16 receives data from the X data memory 20 and the Y data memory 22, whereas the address generation unit 14 provides addresses to the X memory data 20 and the Y data memory 22. In addition to receiving X data and Y data from external memory, the data operation unit 16 receives IO data from an IO interface 23 as illustrated in FIG. 2.
In a normal mode of operation the PCU 12 provides a program address 28 to program memory 18. In response to the program address bus 28, the program memory 18 provides data to the program data bus 38 . This data is available to the PCU 12, AGU 14 or the data operation unit 16.
The data on the program data bus 38 may be stored in an instruction register (IREG) 12B, illustrated in FIG. 2. The instruction stored in the instruction register 12B is decoded, and provides further information 40 to the PC logic 12A, as well as providing control signals to the AGU 14 and the data operation unit 16 to provide for address generation and data operations from X data memory 20 and Y data memory 22. In order to perform the scaling operations 80, 81, and 82 illustrated in FIG. 1, the PCU 12 must access the IO interface 23 via control signals in order to provide as input on the Y data bus 36 gain control information.
FIG. 3 illustrates the prior art PC logic 12A (FIG. 2). FIG. 3 contains a program counter multiplexer (PC Mux) 42 which is coupled to a program counter register 48. The program counter 48 provides a program counter value to an adder 50 and an address multiplexer 46. The program counter register 48 can store an interrupt vector value 26 or an output of the adder 50 based on the PC Mux 42 as illustrated in FIG. 3. The adder 50 performs mathematical operations between the value stored in the program counter register 48 and the output of an offset multiplexer 44. The offset multiplexer 44 provides either a binary value of +1 to provide for sequential incrementing of the program counter register, or a branch offset value 40 for performing branch operations within the digital signal processor 10. An output 28 of address mux 46 is coupled to either the program counter register 48 or the output of the adder 50. The program address 28 is the address used as shown in FIG. 2 to access external program memory 18.
In order to perform operations 73, 74, 76, 77, and 78 of FIG. 1 in software, the following instructions are typically needed: (1) move accumulator to memory or IO; (2) move memory or IO to the accumulator; (3) multiply address register indirect with an immediate value and store the result in the accumulator; (4) the operation of (3) above where the result is added to the accumulator; and (5) load register with an immediate value. Therefore, the software routine 73 through 78 in FIG. 1 can be performed by using five basic instructions. The hardware needed to support these five instructions can be implemented in a digital signal processor in an efficient manner. While operations 73 through 78 of FIG. 1 perform most of the processing needed for the operation of FIG. 1, they do not perform all the functions.
In order to perform the operations 80 through 89 in FIG. 1, a significant number of additional instructions need to be provided for within the hardware of FIG. 2 and FIG. 3. In order to perform the operations in 80 through 89 in FIG. 1 the following instructions are needed: (1) transfer the accumulator to register; (2) mask bits in register; (3) shift register to the right; (4) add an offset to a register; (5) multiply address indirect register 1 by address indirect register 2 and store the result in the accumulator. The addition of these five instructions while performing a small portion of the operations required for the algorithm of FIG. 1, involves significantly complicating the design of the PCU 12 and AGU 14 of the DSP 10 (FIG. 2). These complications include: (1) using five instructions to implement one function. This complicates the control section making it larger; (2) requiring more program memory, as a result of requiring the usage of multiple instructions. This ultimately uses more power and slows execution; (3) requiring a bus connecting the data operation unit 16 to the address generation unit 14; (4) requiring additional arithmetic logic in the address generation unit 14 to implement the instructions for logical anding, adding, and shifting; (5), requiring the multiply instruction to handle indirect addressing capability on both sources instead of just one source, this also significantly complicates the design; (6) implementing (1)-(5) requires longer design and test time.